A typical semiconductor transistor device comprises a gate, which has a conductive element stacked onto a dielectric layer on a semiconductor substrate, and doped regions within the substrate on either side of the gate. The dielectric layer is typically an oxide and is often referred to as the gate oxide. One doped region is referred to as a source, the other as a drain, indicating the direction of current flow. The portion of the substrate beneath the gate oxide and in between the source and drain is referred to as the channel region. Such a transistor is often referred to as a Metal-Oxide-Semiconductor (MOS) transistor.
During operation of a transistor, electrons flow from the source region to the drain region, through the channel region, when an electric field is established between the source and drain regions. Furthermore, the drain-to-substrate junction is reverse biased when a gate voltage equal to or greater than the threshold voltage (Vt) of the transistor is applied to the gate. These conditions can be met, for example, when a ground is applied to the substrate and the source region, and one volt, for example, is applied to the drain region.
A gate voltage applied to the gate attracts electrons to the surface adjacent to the gate oxide of the substrate in the channel region. When a minimum number of electrons have been attracted to the surface of the substrate in the channel region, the electrons form a channel which allows the electrons in the source region to flow to the drain region under the influence of the electric field. The threshold voltage is defined as the minimum gate voltage that must be applied to the gate to attract the minimum number of electrons to the surface of the substrate to form an electrically conductive inversion region in the channel region (i.e., the minimum voltage required to turn the transistor on).
The threshold voltage of the transistor may be altered or adjusted by implanting the surface of the substrate in the channel region with a dopant. For example, in an N-MOS transistor, implanting a p-type dopant decreases the number of electrons that can be accumulated at the surface of the channel region. Since fewer electrons are available, a higher gate voltage is needed to attract the minimum number of electrons that are required to form an inversion layer in the channel region. Such an implant may be referred to as a threshold voltage adjustment implant, a Vt adjustment implant, a Vt implant, or an enhancement implant.
MOS transistors are formed using photolithographic processes according to design rules corresponding to a particular process. The design rules specify, among other things, the minimum length of the channel region. To gain performance advantages and as processing technology advancements have been achieved, the channel length between the source and drain has generally shortened. Furthermore, to minimize the substrate area consumed by a MOS circuit, a typical integrated circuit design is largely implemented with transistors that have the minimum channel length. Since the circuit is largely implemented with transistors that have the minimum channel length, the fabrication process is commonly optimized to adjust the threshold voltages of the transistors which have the minimum channel length. While performance improvement is generally a paramount objective for MOS circuit design, it is common for circuits, in addition to utilizing transistors having minimum channel length, to also require transistors which have channel lengths longer than the minimum. For those transistors with a longer channel length, a lower or higher threshold voltage can be realized when the threshold voltage is optimized for a shorter channel transistor through the use of a single enhancement implant.
To affect different threshold voltages in long channel devices and short channel devices, it is known in the art to utilize multiple Vt adjustment implants requiring separate masks.